A liquid crystal display apparatus which displays a still image is exemplified by a liquid crystal display apparatus including a pixel memory which carries out a display by temporarily retaining image data written to a pixel and carrying out a refresh operation while reversing polarities of the image data. Image data is rewritten to new image data in a pixel every one frame via a data signal line in a normal operation in which a multi-gradation moving image is displayed, whereas image data retained in a pixel memory is used in a memory operation in which a still image is displayed. In view of this, it is unnecessary to supply rewriting image data to a data line while the refresh operation is being carried out.
Accordingly, electric power consumption can be reduced since it is possible in the memory operation to stop an operation of a circuit which drives a scanning signal line and a data signal line. Electric power consumption can also be reduced by a reduction in number of times of charge and discharge of the data signal line having a large capacity and without the need of transmitting, to a controller, image data corresponding to a memory operation period.
Accordingly, a pixel which carries out the memory operation is frequently used for an image display such as a standby display of a mobile phone, the image display being strongly required to be carried out with lower electric power consumption.
FIG. 34 illustrates only a memory circuit part of each pixel structure of a liquid crystal display apparatus including such a pixel memory. In order to cause the each pixel structure to function also as a pixel of the liquid crystal display apparatus, it is only necessary to assume that a liquid crystal capacitor Clc is added to the each pixel structure (see a broken line in FIG. 34). Such a pixel structure is equivalent to, for example, a pixel structure disclosed in Patent Literature 1.
A memory circuit MR100 serving as the memory circuit part includes a switching circuit SW100, a first data retaining section DS101, a data transfer section TS100, a second data retaining section DS102, and a refresh output control section RS100.
The switching circuit SW100 includes a transistor N100 which is an N-channel TFT. The first data retaining section DS101 includes a capacitor Ca100. The data transfer section TS100 includes a transistor N101 which is an N-channel TFT. The second data retaining section DS102 includes a capacitor Cb100. The refresh output control section RS100 includes an inverter INV100 and a transistor N103 which is an N-channel TFT. The inverter INV100 includes a transistor P100 which is a P-channel TFT and a transistor N102 which is an N-channel TFT.
As wires for driving each memory circuit MR100, a data transfer control line DT100, a switch control line SC100, a High voltage supply line PH100, a Low voltage supply line PL100, a refresh output control line RC100, and a capacitor wire CL100 are provided for each row of a pixel matrix, and a data input line IN100 is provided for each column of the pixel matrix.
One and the other of drain/source terminals of a field-effect transistor such as a TFT mentioned above are referred to as a first drain/source terminal and a second drain/source terminal, respectively. Note, however, that the first drain/source terminal and the second drain/source terminal between which a drain terminal and a source terminal are constantly fixed in accordance with a direction in which a current flows are referred to as the drain terminal and the source terminal, respectively. The transistor N100 has a gate terminal which is connected to the switch control line SC100, a first source/drain terminal which is connected to the data input line IN100, and a second source/drain terminal which is connected to a node PIX that is one end of the capacitor Ca100. The other end of the capacitor Ca100 is connected to the capacitor wire CL100.
The transistor N101 has a gate terminal which is connected to the data transfer control line DT100, a first source/drain terminal which is connected to the node PIX, and a second source/drain terminal which is connected to a node MRY that is one end of the capacitor Cb100. The other end of the capacitor Cb100 is connected to the capacitor wire CL100.
An input terminal IP of the inverter INV100 is connected to the node MRY. The transistor P100 has a gate terminal which is connected to the input terminal IP of the inverter INV100, a source terminal which is connected to the High voltage supply line PH100, and a drain terminal which is connected to an output terminal OP of the inverter INV100. The transistor N102 has a gate terminal which is connected to the input terminal IP of the inverter INV100, a drain terminal which is connected to the output terminal OP of the inverter INV100, and a source terminal which is connected to the Low voltage supply line PL100. The transistor N103 has a gate terminal which is connected to the refresh output control line RC100, a first drain/source terminal which is connected to the output terminal OP of the inverter INV100, and a second drain/source terminal which is connected to the node PIX.
Note that, in a case where a pixel structure is constituted as a pixel by adding the liquid crystal capacitor Clc to the memory circuit MR100, the liquid crystal capacitor Clc is connected between the node PIX and a common electrode COM.
Next, operation of the memory circuit MR100 is described below with reference to FIG. 35.
It is assumed in FIG. 35 that the memory circuit MR100 is in a memory operation mode such as a standby state of a mobile phone. An electric potential of binary levels which are High (an active level) and Low (a non-active level) is applied from a driving circuit (not illustrated) to each of the data transfer control line DT100, the switch control line SC100, and the refresh output control line RC100. The High and Low binary levels of a voltage may be individually set for each of these lines. The High and Low binary logic levels are supplied from the driving circuit (not illustrated) to the data input line IN100. An electric potential to be supplied from the High voltage supply line PH100 is equivalent to the High binary logic level, and an electric potential to be supplied from the Low voltage supply line PL100 is equivalent to the Low binary logic level. An electric potential to be supplied from the capacitor wire CL100 may be constant or may change at a given timing. For convenience of explanation, it is assumed here that the electric potential to be supplied from the capacitor wire CL100 is constant.
A writing period T101 and a refresh period T102 are set in the memory operation mode. The writing period T101 is a period in which data to be retained in the memory circuit MR100 is written to the memory circuit MR100 and which has a period t101 and a period t102 that are successive. Since line-sequential writing is carried out with respect to the memory circuit MR100 in the writing period T101, an end timing of the period t101 is set for each row within a period in which corresponding writing data is outputted. An end timing of the period t102, i.e., an end timing of the writing period T101 is identical in all the rows. The refresh period T102 is a period in which the data written to the memory circuit MR100 in the writing period T101 is retained while being refreshed and which has a period t103 through a period t110 that start concurrently in all the rows and are successive.
The switch control line SC100 has a High electric potential in the period t101 of the writing period T101. Each of the data transfer control line DT100 and the refresh output control line RC100 has a Low electric potential. This causes the transistor N100 to turn on. Therefore, a data electric potential (High here) supplied to the data input line IN100 is written to the node PIX. The switch control line SC100 has a Low electric potential in the period t102. This causes the transistor N100 to turn off. Therefore, an electric charge corresponding to the written data electric potential is retained in the capacitor Ca100.
Note here that, in a case where the memory circuit MR100 is constituted only by the capacitor Ca100 and the transistor N100, the node PIX is floating while the transistor N100 is off. In this case, ideally, the electric charge is retained in the capacitor Ca100 so that an electric potential of the node PIX is maintained at High. However, in reality, an off-leakage current occurs in the transistor N100. This causes the electric charge of the capacitor Ca100 to gradually leak to an outside of the memory circuit MR100. The leak of the electric charge of the capacitor Ca100 causes the electric potential of the node PIX to change. Therefore, in a case where the electric charge leaks for a long time, the electric potential of the node PIX changes to an extent that the written data electric potential loses its original function.
In view of the circumstances, the data transfer section TS100, the second data retaining section DS102, and the refresh output control section RS100 are arranged to function to refresh the electric potential of the node PIX, so as to prevent the written data from being lost.
Therefore, the refresh period T102 comes next. The data transfer control line DT100 has a High electric potential in the period t103. This causes the transistor N101 to turn on. Therefore, the capacitor Cb100 is connected in parallel to the capacitor Ca100 via the transistor N101. The capacitor Ca100 is set to have a larger capacitance than the capacitor Cb100. Accordingly, movement of the electric charge between the capacitor Ca100 and the capacitor Cb100 causes an electric potential of the node MRY to be High. A positive electric charge moves from the capacitor Ca100 via the transistor N101 to the capacitor Cb100 until the electric potential of the node PIX becomes equivalent to the electric potential of the node MRY. This causes the electric potential of the node PIX to be lower by a slight amount of voltage of ΔV1 than that obtained in the period t102. However, the electric potential of the node PIX falls within a range of a High electric potential. The data transfer control line DT100 has a Low electric potential in the period t104. This causes the transistor N101 to turn off. Therefore, the electric charge is retained in the capacitor Ca100 so that the electric potential of the node PIX is maintained at High, and the electric charge is retained in the capacitor Cb100 so that the electric potential of the node MRY is maintained at High.
The refresh output control line RC100 has a High electric potential in the period t105. This causes the transistor N103 to turn on. Therefore, the output terminal OP of the inverter INV100 is connected to the node PIX. Since an inverse electric potential (Low here) to the electric potential of the node MRY is supplied to the output terminal OP, the node PIX is charged at the inverse electric potential. The refresh output control line RC100 has a Low electric potential in the period t106. This causes the transistor N103 to turn off. Therefore, the electric charge is retained in the capacitor Ca100 so that the electric potential of the node PIX is maintained at the inverse electric potential.
The data transfer control line DT100 has a High electric potential in the period t107. This causes the transistor N101 to turn on. Therefore, the capacitor Cb100 is connected in parallel to the capacitor Ca100 via the transistor N101. Accordingly, movement of the electric charge between the capacitor Ca100 and the capacitor Cb100 causes the electric potential of the node MRY to be Low. A positive electric charge moves from the capacitor Cb100 via the transistor N101 to the capacitor Ca100 until the electric potential of the node MRY becomes equivalent to the electric potential of the node PIX. This causes the electric potential of the node PIX to be higher by a slight amount of voltage of ΔV2 than that obtained in the period t106. However, the electric potential of the node PIX falls within a range of a Low electric potential.
The data transfer control line DT100 has a Low electric potential in the period t108. This causes the transistor N101 to turn off. Therefore, the electric charge is retained in the capacitor Ca100 so that the electric potential of the node PIX is maintained at Low, and the electric charge is retained in the capacitor Cb100 so that the electric potential of the node MRY is maintained at Low.
The refresh output control line RC100 has a High electric potential in the period t109. This causes the transistor N103 to turn on. Therefore, the output terminal OP of the inverter INV100 is connected to the node PIX. Since an inverse electric potential (High here) to the electric potential of the node MRY is supplied to the output terminal OP, the node PIX is charged at the inverse electric potential. The refresh output control line RC100 has a Low electric potential in the period t110. This causes the transistor N103 to turn off. Therefore, the electric charge is retained in the capacitor Ca100 so that the electric potential of the node PIX is maintained at the inverse electric potential.
Thereafter, the period t103 through the period t110 are repeated in the refresh period T102 until the next writing period T101 comes. In the period t105, the electric potential of the node PIX is refreshed to the inverse electric potential. In the period t109, the electric potential of the node PIX is refreshed to the electric potential obtained during writing. Note that, in a case where the data electric potential of Low is written to the node PIX in the period t101 of the writing period T101, an electric potential waveform of the node PIX is obtained by inverting an electric potential waveform of FIG. 35.
As described earlier, the memory circuit MR100 is arranged such that in accordance with a data inversion method, written data is retained while being refreshed. Assume that the liquid crystal capacitor Clc is added to the memory circuit MR100. In a case where an electric potential of the common electrode COM is reversed between High and Low at a timing at which data is refreshed, black display data or white display data can be refreshed while its polarities are being reversed.